The problem with LVS is that in order for it to operate properly, one needs in-depth knowledge of the how the layout CAD program extracts netlists, how the schematics CAD program extracts netlists, and how the LVS program handles and manipulates both. This document is meant to help with the above tasks, using the following programs: AnaLog for schematic entry, LEdit for layout, and Ledit LVS for comparison.
The MODEL=xxx should contain the name of the new device IN LOWER CASE. Notice that there is a line of the form FloatingGate= or Tun= for every port that you want the device to ultimately have.
For example, here is how I did the tunneling junction (two ports):
device = SUBCKT( RLAYER=real other transistor; FloatingGate=poly not resistor; Tun=Well not resistor; MODEL=tun; )Make sure your ledit setup points to this .ext file when you go to extract.
Next, you have to modify your .elm file to tell LEDIT what to call the pins it extracts. Notice that the text after the || D must be exactly the same as the MODEL= name from above and also in lower case. For example, the tunneling node added this line:
|| D tun FG TN;Make sure to modify whatever shell script you are using for leditlvs (probably /usr/physcmp/bin/leditlvs) to reference the .elm file you modified above. For example, my shell script runs Jeff Dickson's MOSCAP fixing filter and then uses:
exec lvs -vf -nrcl -e ./roweis.elm $1 $2to call the actual lvs program.
Okay, now LEDIT should extract the junctions fine and also lvs should find them OK. So the last (and hardest) thing left is analog.
To do this, first you need to make a .spc file for the new analog element. This file needs to be called xxx.spc where xxx is the name that has been used all along, again ALL IN LOWER CASE. For example, here is the file tun.spc that I used for the tunneling node:
.SUBCKT tun FG TUN .ENDS tun X1 FG TUN tun .ENDNotice three things here. First, the name that appears after SUBCKT and at the end of the X1 line has to be the same as the filename (without the .spc extension of course), and (you guessed it) in lower case. Also, the port names (FG and TUN in this case) have to be exactly the same and in the same order as in the .elm file from up top. Lastly, the subcircuit definition may in fact be totally empty, defining nothing but the pins to match the ports. That's totally cool, in fact that is exactly the way it should be for it to lvs properly since LEDIT will only extract an xxx model and nothing inside it.
Next, you need to make a new gate using loged. Give the gate the same name you have been using all along, except that loged only speaks capital letters. Don't worry, it will still work. Save this gate with all of your others in a something.gate file which gets loaded when you load analog. Then go to CAT, then LIBR and grab the gate to put it in your tray. Then you can add it to your schematic. If you save your schematic with the new gate in it, and you do not change your analog setup to automatically load in that gate, then analog will complain that it cannot find the gate every time you load a file that uses it. So its best to have the gate loaded by default.
Now, in analog, you need to do two things. First, you need to
include the label